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functional block diagrams rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a lc 2 mos dual 12-bit dacports ad7237a/ad7247a features complete dual 12-bit dac comprising two 12-bit cmos dacs on-chip voltage reference output amplifiers reference buffer amplifiers improved ad7237/ad7247: 12 v to 15 v operation faster interface C30 ns typ data setup time parallel loading structure: ad7247a (8+4) loading structure: ad7237a single or dual supply operation low power165 mw typ in single supply one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 product highlights 1. the ad7237a/ad7247a is a dual 12-bit dacport ? on a single chip. this single chip design and small package size offer considerable space saving and increased reliability over multichip designs. 2. the improved interface times of the parts allow easy, direct interfacing to most modern microprocessors, whether they have 8-bit or 16-bit data bus structures. 3. the ad7237a/ad7247a features a wide power supply range allowing operation from 12 v supplies. dacport is a registered trademark of analog devices, inc. general description the ad7237a/ad7247a is an enhanced version of the industry standard ad7237/ad7247. improvements include operation from 12 v to 15 v supplies, faster interface times and better reference variations with v dd . additional features include faster settling times. the ad7237a/ad7247a is a complete, dual, 12-bit, voltage output digital-to-analog converter with output amplifiers and zener voltage reference on a monolithic cmos chip. no exter- nal user trims are required to achieve full specified performance. both parts are microprocessor compatible, with high speed data latches and interface logic. the ad7247a accepts 12-bit paral- lel data which is loaded into the respective dac latch using the wr input and a separate chip select input for each dac. the ad7237a has a double buffered interface structure and an 8-bit wide data bus with data loaded to the respective input latch in two write operations. an asynchronous ldac signal on the ad7237a updates the dac latches and analog outputs. a ref out/ref in function is provided which allows either the on-chip 5 v reference or an external reference to be used as a reference voltage for the part. for single supply operation, two output ranges of 0 v to +5 v and 0 v to +10 v are available, while these two ranges plus an additional 5 v range are avail- able with dual supplies. the output amplifiers are capable of de- veloping +10 v across a 2 k w load to gnd. the ad7237a/ad7247a is fabricated in linear compatible cmos (lc 2 mos), an advanced, mixed technology process that combines precision bipolar circuits with low power cmos logic. both parts are available in a 24-pin, 0.3" wide plastic and hermetic dual-in-line package (dip) and are also packaged in a 24-lead small outline (soic) package.
rev. 0 C2C ad7237a/ad7247aCspecifications (v dd = +12 v to +15 v, 1 v ss = 0 v or C12 v to C15 v, 1 agnd = dgnd = 0 v [ad7237a], gnd = 0 v [ad7247a], ref in = +5 v, parameter a 2 b 2 t 2 units test conditions/comments static performance resolution 12 12 12 bits relative accuracy 3 1 1/2 1/2 lsb max differential nonlinearity 3 0.9 0.9 0.9 lsb max guaranteed monotonic unipolar offset error 3 3 3 4 lsb max v ss = 0 v or C12 v to C15 v 4 . dac latch contents all 0s bipolar zero error 3 6 4 6 lsb max v ss = C12 v to C15 v 4 . dac latch contents 1000 0000 0000 full-scale error 3, 5 5 5 6 lsb max full-scale mismatch 5 1 1 1 lsb typ reference output ref out 4.97/5.03 4.97/5.03 4.95/5.05 v min/max reference temperature coefficient 25 25 25 ppm/ c typ reference load change ( d ref out vs. d i) C1 C1 C1 mv max reference load current change (0-100 m a) reference input reference input range 4.75/5.25 4.75/5.25 4.75/5.25 v min/max 5 v 5% input current 6 5 5 5 m a max digital inputs input high voltage, v inh 2.4 2.4 2.4 v min input low voltage, v inl 0.8 0.8 0.8 v max input current i in (data inputs) 10 10 10 m a max v in = 0 v to v dd input capacitance 6 8 8 8 pf max analog outputs output range resistors 15/30 15/30 15/30 k w min/max output voltage ranges 7 +5, +10 +5, +10 v single supply; (v ss = 0 v) output voltage ranges 7 +5, +10, 5 +5, +10, 5 +5, +10, 5 dual supply; (v ss = C12 v to C15 v 4 ) dc output impedance 0.5 0.5 0.5 w typ ac characteristics 6 voltage output settling time settling time to within 1/2 lsb of final value positive full-scale change 8 8 10 m s max dac latch all 0s to all 1s. typically 5 m s negative full-scale change 8 8 10 m s max dac latch all 1s to all 0s. typically 5 m s v ss = C12 v to C15 v 4 . digital-to-analog glitch impulse 3 30 30 30 nv secs typ dac latch contents toggled between all 0s and all 1s digital feedthrough 3 10 10 10 nv secs typ digital crosstalk 3 30 30 30 nv secs typ power requirements v dd +10.8/+16.5 +11.4/+15.75 +11.4/+15.75 v min/max for specified performance unless otherwise stated v ss C10.8/C16.5 C11.4/C15.75 C11.4/C15.75 v min/max for specified performance unless otherwise stated i dd 15 15 15 ma max output unloaded. typically 10 ma i ss (dual supplies) 5 5 5 ma max output unloaded. typically 3 ma notes 1 power supply tolerance is 10% for a version and 5% for b and t versions. 2 temperature ranges are as follows: a, b versions, C40 c to +85 c; t version, C55 c to +125 c. 3 see terminology. 4 with appropriate power supply tolerances. 5 measured with respect to ref in and includes unipolar/bipolar offset error. 6 sample tested @ +25 c to ensure compliance. 7 0 v to +10 v range is only available with v dd 3 14.25 v. specifications subject to change without notice. r l = 2 k w , c l = 100 pf. all specifications t min to t max unless otherwise noted.)
ad7237a/ad7247a rev. 0 C3C timing characteristics 1, 2 limit at t min , t max limit at t min , t max parameter (a, b versions) (t version) units conditions/comments t 1 0 0 ns min cs to wr setup time t 2 0 0 ns min cs to wr hold time t 3 80 100 ns min wr pulse width t 4 80 80 ns min data valid to wr setup time t 5 4 10 10 ns min data valid to wr hold time t 6 0 0 ns min address to wr setup time t 7 0 0 ns min address to wr hold time t 8 5 80 100 ns min ldac pulse width notes 1 sample tested at +25 c to ensure compliance. all input signals are specified with tr = tf = 5 ns (10% to 90% of 5 v) and timed from a voltage level of 1.6 v. 2 see figures 5 and 7. 3 power supply tolerance is 10% for a version and 5% for b and t versions. 4 if 0 ns < t 2 < 10 ns, add t 2 to t 5 . if t 2 3 10 ns, add 10 ns to t 5 . 5 ad7237a only. absolute maximum ratings 1 (t a = +25 c unless otherwise noted) v dd to gnd (ad7247a) . . . . . . . . . . . . . . . . C0.3 v to +17 v v dd to agnd, dgnd (ad7237a) . . . . . . . . C0.3 v to +17 v v dd to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +34 v agnd to dgnd (ad7237a) . . . . . . . . . C0.3 v, v dd +0.3 v v outa , 2 v outb 2 to agnd (gnd) . . v ss C0.3 v to v dd +0.3 v ref out to agnd (gnd) . . . . . . . . . . . . . . . . . 0 v to v dd ref in to agnd (gnd) . . . . . . . . . . C0.3 v to v dd +0.3 v digital inputs to dgnd (gnd) . . . . . . C0.3 v to v dd +0.3 v operating temperature range industrial (a, b versions) . . . . . . . . . . . . . C40 c to +85 c extended (t version) . . . . . . . . . . . . . . . C55 c to +125 c storage temperature range . . . . . . . . . . . . C65 c to +150 c lead temperature (soldering, 10 secs) . . . . . . . . . . . . +300 c power dissipation (any package) to +75 c . . . . . . . 1000 mw derates above +75 c by . . . . . . . . . . . . . . . . . . . . . 10 mw/ c notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 short-circuit current is typically 80 ma. the outputs may be shorted to voltages in this range provided the power dissipation of the package is not exceeded. ordering guide relative temperature accuracy package model 1 range (lsb) option 2 ad7237aan C40 c to +85 c 1 max n-24 ad7237abn C40 c to +85 c 1/2 max n-24 ad7237aar C40 c to +85 c 1 max r-24 ad7237abr C40 c to +85 c 1/2 max r-24 ad7237atq C55 c to +125 c 1/2 max q-24 ad7247aan C40 c to +85 c 1 max n-24 ad7247abn C40 c to +85 c 1/2 max n-24 ad7247aar C40 c to +85 c 1 max r-24 ad7247abr C40 c to +85 c 1/2 max r-24 ad7247atq C55 c to +125 c 1/2 max q-24 notes 1 to order mil-std-883, class b processed parts, add /883b to part number. contact local sales office for military data sheet and availability. 2 n = plastic dip; q = cerdip; r = small outline (soic). caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7237a/ad7247a features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device (v dd = +12 v to +15 v, 3 v ss = 0 v or C12 v to C15 v, 3 agnd = dgnd = 0 v [ad7237a], gnd = 0 v [ad7247a])
ad7237a/ad7247a rev. 0 C4C ad7237a pin function description (dip pin numbers) pin mnemonic description 1 ref ina voltage reference input for dac a. the reference voltage for dac a is applied to this pin. it is internally buffered before being applied to the dac. the nominal reference voltage for correct operation of the ad7237a is 5 v. 2 ref out voltage reference output. the internal 5 v analog reference is provided at this pin. to operate the part with internal reference, ref out should be connected to ref ina, ref inb. 3 ref inb voltage reference input for dac b. the reference voltage for dac b is applied to this pin. it is internally buffered before being applied to the dac. the nominal reference voltage for correct operation of the ad7237a is 5 v. 4r ofsb output offset resistor for dac b. this input configures the output ranges for dac b. it is connected to v outb for the +5 v range, to agnd for the +10 v range and to ref inb for the 5 v range. 5v outb analog output voltage from dac b. this is the buffer amplifier output voltage. three different output voltage ranges can be chosen: 0 v to +5 v, 0 v to +10 v and 5 v. the amplifier is capable of developing +10 v across a 2 k w resistor to gnd. 6 agnd analog ground. ground reference for dacs, reference and output buffer amplifiers. 7 db7 data bit 7. 8-10 db6-db4 data bit 6 to data bit 4. 11 db3 data bit 3/data bit 11 (msb). 12 dgnd digital ground. ground reference for digital circuitry. 13 db2 data bit 2/data bit 10. 14 db1 data bit 1/data bit 9. 15 db0 data bit 0 (lsb)/data bit 8. 16 a0 address input. least significant address input for input latches. a0 and a1 select which of the four input latches data is written to (see table ii). 17 a1 address input. most significant address input for input latches. 18 cs chip select. active low logic input. the device is selected when this input is active. 19 wr write input. wr is an active low logic input which is used in conjunction with cs , a0 and a1 to write data to the input latches. 20 ldac load dac. logic input. a new word is loaded into the dac latches from the respective input latches on the falling edge of this signal. 21 v dd positive supply (+12 v to +15 v). 22 v outa analog output voltage from dac a. this is the buffer amplifier output voltage. three different output voltage ranges can be chosen: 0 v to +5 v, 0 v to +10 v and 5 v. the amplifier is capable of developing +10 v across a 2 k w resistor to gnd. 23 v ss negative supply (0 v or C12 v to C15 v). 24 r ofsa output offset resistor for dac a. this input configures the output ranges for dac a. it is connected to v outa for the +5 v range, to agnd for the +10 v range and to ref ina for the 5 v range.
ad7237a/ad7247a rev. 0 C5C ad7247a pin function description (dip pin numbers) pin mnemonic description 1 ref out voltage reference output. the internal 5 v analog reference is provided at this pin. to operate the part with internal reference, ref out should be connected to ref in. 2r ofsb output offset resistor for dac b. this input configures the output ranges for dac b. it is connected to v outb for the +5 v range, to gnd for the +10 v range and to ref in for the 5 v range. 3v outb analog output voltage from dac b. this is the buffer amplifier output voltage. three different output voltage ranges can be chosen: 0 v to +5 v, 0 v to +10 v and 5 v. the amplifier is capable of developing +10 v across a 2 k w resistor to gnd. 4 db11 data bit 11 (msb). 5 db10 data bit 10. 6 gnd ground. ground reference for all on-chip circuitry. 7C15 db9-db1 data bit 9 to data bit 1. 16 db0 data bit 0 (lsb). 17 csb chip select input for dac b. active low logic input. dac b is selected when this input is active. 18 csa chip select input for dac a. active low logic input. dac a is selected when this input is active. 19 wr write input. wr is an active low logic input which is used in conjunction with csa and csb to write data to the dac latches. 20 v dd positive supply (+12 v to +15 v). 21 v outa analog output voltage from dac a. this is the buffer amplifier output voltage. three different output voltage ranges can be chosen: 0 v to +5 v, 0 v to +10 v and 5 v. the amplifier is capable of developing +10 v across a 2 k w resistor to gnd. 22 v ss negative supply (0 v or C12 v to C15 v). 23 r ofsa output offset resistor for dac a. this input configures the output ranges for dac a. it is connected to v outa for the +5 v range, to gnd for the +10 v range and to ref in for the 5 v range. 24 ref in voltage reference input. the common reference voltage for both dacs is applied to this pin. it is internally buffered before being applied to both dacs. the nominal reference voltage for correct operation of the ad7247a is 5 v. ad7237a pin configuration dip and soic ad7247a pin configuration dip and soic
ad7237a/ad7247a rev. 0 C6C terminology relative accuracy (linearity) relative accuracy, or endpoint linearity, is a measure of the maximum deviation of the dac transfer function from a straight line passing through the endpoints of the transfer func- tion. it is measured after allowing for zero and full-scale errors and is expressed in lsbs or as a percentage of full-scale read ing. differential nonlinearity differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb or less over the operating temperature range ensures monotonicity. single supply linearity and gain error the output amplifiers of the ad7237a/ad7247a can have true negative offsets even when the part is operated from a single +12 v to +15 v supply. however, because the negative supply rail (v ss ) is 0 v, the output cannot actually go negative. instead, when the output offset voltage is negative, the output voltage sits at 0 v, resulting in the transfer function shown in figure 1. this knee is an offset effect, not a linearity error, and the transfer function would have followed the dotted line if the out- put voltage could have gone negative. figure 1. effect of negative offset (single supply) normally, linearity is measured between zero (all 0s input code) and full scale (all 1s input code) after offset and full scale have been adjusted out or allowed for, but this is not possible in single supply operation if the offset is negative, due to the knee in the transfer function. instead, linearity of the ad7237a/ ad7247a in the unipolar mode is measured between full scale and the lowest code which is guaranteed to produce a positive output voltage. this code is calculated from the maximum specification for negative offset, i.e., linearity is measured be- tween codes 3 and 4095. unipolar offset error unipolar offset error is the measured output voltage from v outa or v outb with all zeros loaded into the dac latches when the dacs are configured for unipolar output. it is a com- bination of the offset errors of the dac and output amplifier. bipolar zero error bipolar zero error is the voltage measured at v outa or v outb when the dac is connected in the bipolar mode and loaded with code 2048. it is due to a combination of offset errors in the dac, amplifier offset and mismatch in the application resistors around the amplifier. full-scale error full-scale error is a measure of the output error when the amplifier output is at full scale (for the bipolar output range full scale is either positive or negative full scale). it is measured with respect to the reference input voltage and includes the offset errors. digital feedthrough digital feedthrough is the glitch impulse injected for the digital inputs to the analog output when the data inputs change state, but the data in the dac latches is not changed. for the ad7237a it is measured with ldac held high. for the ad7247a it is measured with csa and csb held high. digital crosstalk digital crosstalk is the glitch impulse transferred to the output of one converter due to a change in digital code to the dac latch of the other converter. it is specified in nv secs. digital-to-analog glitch impulse this is the voltage spike that appears at the output of the dac when the digital code changes before the output settles to its fi- nal value. the energy in the glitch is specified in nv secs and is measured for a 1 lsb change around the major carry transition (0111 1111 1111 to 1000 0000 0000).
ad7237a/ad7247a rev. 0 C7C power supply current vs. temperature noise spectral density vs. frequency single supply sink current vs. output voltage dac-to-dac linearity matching power supply rejection ratio vs. frequency linearity vs. power supply voltage
ad7237a/ad7247a rev. 0 C8C circuit information d/a section the ad7237a/ad7247a contains two 12-bit voltage-mode d/a converters consisting of highly stable thin film resistors and high speed nmos single-pole, double-throw switches. the output voltage from the converters has the same polarity as the refer- ence voltage, ref in, allowing single supply operation. the simplified circuit diagram for one of the d/a converters is shown in figure 2. the ref in voltage is internally buffered by a unity gain amplifier before being applied to the d/a converters. the d/a converters are configured and scaled for a 5 v reference and the device is tested with 5 v applied to ref in. figure 2. d/a simplified circuit diagram internal reference the ad7237a/ad7247a has an on-chip temperature compen- sated buried zener reference (see figure 3) which is factory trimmed to 5 v 30 mv ( 50 mv for t version). the reference voltage is provided at the ref out pin. this reference can be used to provide the reference voltage for the d/a converter (by connecting the ref out pin to the ref in pin) and the offset voltage for bipolar outputs (by connecting ref out to r ofs ). the reference voltage can also be used as a reference for other components and is capable of providing up to 500 m a to an ex- ternal load. the maximum recommended capacitance on ref out for normal operation is 50 pf. if the reference is required for external use, it should be decoupled to agnd (gnd) with a 200 w resistor in series with parallel combination of a 10 m f tantalum capacitor and a 0.1 m f ceramic capacitor. figure 3. internal reference external reference in some applications, the user may require a system reference or some other external reference to drive the ad7237a/ ad7247a reference input. references such as the ad586 5 v reference provide the ideal external reference source for the ad7237a/ ad7247a (see figure 9). op amp section the output of the voltage-mode d/a converter is buffered by a noninverting cmos amplifier. the r ofs input allows different output voltage ranges to be selected. the buffer amplifier is ca- pable of developing +10 v across a 2 k w load to gnd. the output amplifier can be operated from a single +12 v to +15 v supply by tying v ss = 0 v. the amplifier can also be operated from dual supplies ( 12 v to 15 v) to allow a bipolar output range of C5 v to +5 v. the advantages of having dual supplies for the unipolar output ranges are faster settling time to voltages near 0 v, full sink capability of 2.5 ma maintained over the en- tire output range and the elimination of the effects of negative offsets on the transfer characteristic (outlined previously). a plot of the single supply output sink capability of the amplifier is shown in the typical performance graphs section. interface logic informationad7247a table i shows the truth table for ad7247a operation. the part contains a single, parallel 12-bit latch for each dac. it can be treated as two independent dacs, each with its own cs input and a common wr input. csa and wr control the loading of data to the dac a latch while csb and wr control the loading of the dac b latch. if csa and csb are both low, with wr low, the same data will be written to both dac latches. all con- trol signals are level triggered and therefore either or both latches can be made transparent. input data is latched to the re- spective latch on the rising edge of wr . figure 4 shows the in- put control logic for the ad7247a, while the write cycle timing diagram for the part is shown in figure 5. figure 4. ad7247a input control logic figure 5. ad7247a write cycle timing diagram
ad7237a/ad7247a rev. 0 C9C figure 6. ad7237a input control logic table ii. ad7237a truth table cs wr a1 a0 ldac function 1 x x x 1 no data transfer x 1 x x 1 no data transfer 0 0 0 0 1 dac a ls input latch transparent 0 0 0 1 1 dac a ms input latch transparent 0 0 1 0 1 dac b ls input latch transparent 0 0 1 1 1 dac b ms input latch transparent 1 1 x x 0 dac a and dac b dac latches updated simultaneously from the respective input latches x = dont care. however, care must be taken while exercising ldac during a write cycle. if an ldac operation overlaps a cs and wr op- eration, there is a possibility of invalid data being latched to the output. to avoid this, ldac must remain low after cs or wr return high for a period equal to or greater than t 8 , the mini- mum ldac pulse width. figure 7. ad7237a write cycle timing diagram table i. ad7247a truth table csa csb wr function x x 1 no data transfer 1 1 x no data transfer 0 1 0 dac a latch transparent 1 0 0 dac b latch transparent 0 0 0 both dac latches transparent x = dont care interface logic informationad7237a the input loading structure on the ad7237a is configured for interfacing to microprocessors with an 8-bit-wide data bus. the part contains two 12-bit latches per dacan input latch and a dac latch. each input latch is further subdivided into a least significant 8-bit latch and a most significant 4-bit latch. only the data held in the dac latches determines the outputs from the part. the input control logic for the ad7237a is shown in figure 6, while the write cycle timing diagram is shown in figure 7. cs , wr , a0 and a1 control the loading of data to the input latches. the eight data inputs accept right-justified data. data can be loaded to the input latches in any sequence. provided that ldac is held high, there is no analog output change as a result of loading data to the input latches. address lines a0 and a1 determine which latch data is loaded to when cs and wr are low. the selection of the input latches is shown in the truth table for ad7237a operation in table ii. the ldac input controls the transfer of 12-bit data from the input latches to the dac latches. both dac latches, and hence both analog outputs, are updated at the same time. the ldac signal is level triggered, and data is latched into the dac latch on the rising edge of ldac . the ldac input is asynchronous and independent of wr . this is useful in many applications especially in the simultaneous updating of multiple ad7237as.
ad7237a/ad7247a rev. 0 C10C applying the ad7237a/ad7247a the internal scaling resistors provided on the ad7237a/ ad7247a allow several output voltage ranges. the part can produce unipolar output ranges of 0 v to +5 v or 0 v to +10 v and a bipolar output range of 5 v. connections for the various ranges are outlined below. since each dac has its own r ofs input the two dacs on each part can be set up for different output ranges. unipolar (0 v to +10 v) configuration the first of the configurations provides an output voltage range of 0 v to +10 v. this is achieved by connecting the output off- set resistor, r ofsa , or r ofsb , to agnd (gnd for ad7247a). in this configuration, the ad7237a/ad7247a can be operated from single or dual supplies. figure 8 shows the connection dia- gram for unipolar operation for dac a of the ad7237a, while the table for output voltage versus digital code in the dac latch is shown in table iii. similar connections apply to the ad7247a. figure 8. unipolar (0 to +10 v) configuration table iii. unipolar code table (0 to +10 v range) dac latch contents msb lsb analog output, v out 1111 1111 1111 +2 ? ref in (4095/4096) 1000 0000 0001 +2 ? ref in (2049/4096) 1000 0000 0000 +2 ? ref in (2048/4096) = +ref in 0111 1111 1111 +2 ? ref in (2047/4096) 0000 0000 0001 +2 ? ref in (1/4096) 0000 0000 0000 0 v note: 1 lsb = ref in/2048. unipolar (0 v to +5 v) configuration the 0 v to +5 v output voltage range is achieved by tying r ofsa or r ofsb to v outa or v outb . once again, the ad7237a/ ad7247a can be operated single supply or from dual supplies. the table for output voltage versus digital code is as in table iii, with 2 ? ref in replaced by ref in. note, for this range, 1 lsb = ref in ? (2 C12 ) = (ref in/4096). bipolar configuration the bipolar configuration for the ad7237a/ad7247a, which gives an output range of C5 v to +5 v, is achieved by connect- ing r ofsa , or r ofsb , to ref in. the ad7237a/ad7247a must be operated from dual supplies to achieve this output voltage range. figure 9 shows the connection diagram for bipolar opera- tion for dac a of the ad7247a. an ad586 provides the refer- ence voltage for the dac but this could be provided by the on-chip reference by connecting ref out to ref in. the code table for bipolar operation is shown in table iv. similar connections apply for the ad7237a. figure 9. bipolar configuration table iv. bipolar code table dac latch contents msb lsb analog output, v out 1111 1111 1111 +ref in ? (2047/2048) 1000 0000 0001 +ref in ? (1/2048) 1000 0000 0000 0 v 0111 1111 1111 Cref in ? (1/2048) 0000 0000 0001 Cref in ? (2047/2048) 0000 0000 0000 Cref in ? (2048/2048) = Cref in note: 1 lsb = ref in/2048.
ad7237a/ad7247a rev. 0 C11C microprocessor interfacingad7247a figures 10 to 12 show interfaces between the ad7247a and the adsp-2101 dsp processor and the 8086 and 68000 16-bit microproc essors. in all three interfaces, the ad7247a is memory-mapped with a separate memory address for each dac. ad7247aadsp-2101 interface figure 10 shows an interface between the ad7247a and the adsp-2101. the 12-bit word is written to the selected dac latch of the ad7247a in a single instruction, and the analog output responds immediately. depending on the clock fre- quency of the adsp-2101, either one or two wait states will have to be programmed into the data memory wait state control register of the adsp-2101. figure 10. ad7247a to adsp-2101 interface ad7247a8086 interface figure 11 shows an interface between the ad7247a and the 8086 microprocessor. the 12-bit word is written to the selected dac latch of the ad7247a in a single mov instruction, and the analog output responds immediately. figure 11. ad7247a to 8086 interface ad7247amc68000 interface interfacing between the ad7247a and the mc68000 micropro- cessor is achieved using the circuit of figure 12. once again, the 12-bit word is written to the selected dac latch of the ad7247a in a single move instruction. csa and csb have to be and-gated to provide a dtack signal for the mc68000 when either dac latch is selected. figure 12. ad7247a to mc68000 interface microprocessor interfacingad7237a figures 13 to 15 show the ad7237a configured for interfacing to microprocessors with 8-bit databus systems. in all cases, data is right-justified, and the ad7237a is memory-mapped with the two lowest address lines of the microprocessor address bus driv- ing the a0 and a1 inputs of the converter. ad7237a8085a/8088 interface figure 13 shows the connection diagram for interfacing the ad7237a to both the 8085a and the 8088. this scheme is also suited to the z80 microprocessor, but the z80 address/ databus does not have to be demultiplexed. the ad7237a requires five separate memory addresses, one for the each ms latch and one for each ls latch and one for the common ldac input. data is written to the respective input latch in two write operations. figure 13. ad7237a to 8085a/8088 interface
ad7237a/ad7247a rev. 0 C12C c1744C24C3/93 printed in u.s.a. either high byte or low byte data can be written first to the in- put latch. a write to the ad7237a dac latch address transfers the data from the input latches to the respective dac latches and updates both analog outputs. alternatively, the ldac in- put can be asynchronous or can be common to a number of ad7237as for simultaneous updating of a number of voltage channels. ad7237a68008 interface an interface between the ad7237a and the 68008 is shown in figure 14. in the diagram shown, the ldac is derived from an asynchronous ldac signal, but this can be derived from the address decoder as in the previous interface diagram. figure 14. ad7237a to 68008 interface ad7237a6502/6809 interface figure 15 shows an interface between the ad7237a and the 6502 or 6809 microprocessor. the procedure for writing data to the ad7237a is as outlined for the 8085a/8088 interface. for the 6502 microprocessor, the f 2 clock is used to generate the wr , while for the 6809 the e signal is used. figure 15. ad7237a to 6502/6809 interface outline dimensions dimensions shown in inchcs and (mm). plastic dip (n-24) cerdip (q-24) soic (r-24)

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